[BidClub_]
SemiAnalysis · · 78 min

AI Chip & Silicon Round-up 2026

Jordan NanosRay WangMalcolm SplitterJoey Brookhart

YouTube ↗
TL;DR
  • NVIDIA's Vera Rubin VR200 is called the most anticipated release of 2026, and the narrator expects it to “very likely once again top the charts.” Built on TSMC's N3B with HBM4, a single package targets 35 petaflops of FP4 and 288 GB at 22 TB/s, scaled into the NVL72 rack via NVIDIA's NVLink scale-up network—with the caveat that 22 TB/s is “the speed NVIDIA is targeting.”
  • AMD's 2026 could be a turning point—conditional on execution: “if MI455X and the Helios Rack are on time.” CDNA 5, 320 billion transistors in a mix of 12 2-nanometer and 3-nanometer logic chiplets connected via advanced 3.5D packaging, and the headline edge is memory: 432 GB of next-generation HBM4 at nearly 20 TB/s, an advantage that holds “at least until Rubin Ultra, which will come with a full terabyte of HBM.”
  • The structural call of the episode: “More and more inference is moving away from NVIDIA to custom silicon.” Microsoft's Maia 200 (140B transistors, 216 GB HBM3E, over 5 and 10 petaflops at FP8 and FP4, respectively) will run future ChatGPT models; Meta's MTIA v3 is very likely to use HBM and “offers good margins,” so external hardware can handle training while internal inference goes in-house.
  • Trainium 3 is flagged as a top contender for future large-scale deployment, based on Trainium 2's footprint. Hundreds of thousands of Trainium 2 chips already sit in AWS's Canton and New Carlisle data centers; Anthropic's Claude Code was trained on and runs on Trainium, and “OpenAI will use 2 GW of Trainium compute starting this year.”
  • Google's Ironwood (TPU v7) is the efficiency heavyweight if external customers can use it as well as Google can. 192 GB HBM3E, likely 100B+ transistors, and optical circuit switches—“tiny physical mirrors”—linking superpods of up to 9,216 TPUs.
  • Qualcomm's LPDDR bet might have been a great idea a year ago, but memory prices are “skyrocketing across the board,” including LPDDR5X. The AI 200 (768 GB LPDDR5X) is unlikely to make waves, but the AI 250 is supposed to bring a compute-near-memory architecture that, according to Qualcomm, delivers a 10x effective-bandwidth gain with LPDDR6—“don't put on your party hats just yet, but do keep Qualcomm in mind.”
  • The SRAM outliers get respect, not conviction: NVIDIA thought Groq's deterministic LPU “was worth about 20 billion dollars,” while Cerebras's WSE3 with 44 GB of on-wafer SRAM “isn't really cutting it anymore,” even if it is SRAM. Intel's Jaguar Shores (18A, 288 GB HBM4) looks competitive on paper, but it does not seem targeted for 2026 and might be a 2027 product.
Digest · the substance, structured for research

The reference transcript presents a single-narrator scripted rundown; attribution below is to that narrator. The narrator frames 2026 as a massive AI-hardware year—covering GPUs, ASICs and beyond—and says the industry is no longer emerging, citing Google's TPU launch in 2015 and NVIDIA's first Tensor Core GPU in 2017.

1. Vera Rubin vs. Helios — memory capacity is the new battleground

  • The narrator's framing on NVIDIA: VR200 on TSMC's N3B with HBM4 delivers 35 PFLOPS FP4 and 288 GB at a targeted 22 TB/s per package, and in the NVL72 rack “will very likely once again top the charts. Or will it?”
  • The hedge that matters: MI455X (320B transistors, 432 GB of next-generation HBM4, ~20 TB/s) has a memory advantage, “at least until Rubin Ultra, which will come with a full terabyte of HBM.” AMD's 2026 could be a turning point if MI455X and the Helios Rack are on time.
  • Intel's Jaguar Shores (18A, 175B transistors, 288 GB HBM4) reads competitive on paper, but it does not seem targeted for 2026 and might be a 2027 product. Intel must prove both the silicon and the proper software support.

2. Hyperscaler ASICs are pulling inference off NVIDIA

  • The through-line: “More and more inference is moving away from NVIDIA to custom silicon.” Maia 200—around 825 mm², 140B transistors, 216 GB HBM3E, and over 5 PFLOPS FP8 and 10 PFLOPS FP4—will run future ChatGPT models.
  • Meta's MTIA v3 logic as told: Meta “knows exactly what its internal workloads need”—AI chatbots as well as recommendation models, not AGI—so its own inference silicon offers good margins and lets Meta use external hardware to train new models. Full specifications are not known, but the chip is very likely to use TSMC's N3P, more than 100B transistors, and HBM memory; previous MTIA versions used LPDDR5X.
  • Trainium 3 is the top contender for future large-scale deployment: it combines training and inference, while hundreds of thousands of Trainium 2 chips are already in AWS's Canton and New Carlisle data centers. Claude Code was trained on and runs on Trainium, and OpenAI will use 2 GW starting this year.

3. Google's decade head start rides on optical switching

  • Ironwood (TPU v7, N3E, very likely more than 100B transistors, and 192 GB HBM3E) is built to run Gemini inference, but the “superpower” is optical circuit switches—physical mirrors enabling superpods of up to 9,216 TPUs.
  • TPUs were used only by Google until now; Ironwood becomes “a heavyweight for efficient and low-cost inference” only if external customers can use them as well as Google can.

4. Qualcomm's memory gamble and the SRAM contrarians

  • Qualcomm's recent 1,024-chip AI 100 cluster was a small deployment that “doesn't matter in 2026.” Its AI 200 chose LPDDR5X instead of supply-constrained HBM—a bet that might have been great a year ago, but memory prices are “skyrocketing across the board,” including LPDDR5X. AI 200 is unlikely to make major waves this year. Hope shifts to AI 250's compute-near-memory design: according to Qualcomm, a claimed 10x effective-bandwidth jump with fast next-generation LPDDR6.
  • Groq—“the one with a Q, not a K”—trades memory for determinism: 230 MB of SRAM, no external memory, and clockwork execution that “basically eliminates the latency problems that GPUs have to deal with,” though “you need to connect a lot of LPUs to run even smaller models. Everything is a trade-off.” NVIDIA acquired Groq and thought it was worth about $20B. A 2026 product is uncertain; the second-generation LPU based on Samsung's 4-nanometer process is the one to watch.
  • Cerebras's wafer-scale WSE3 (4T transistors, 44 GB of SRAM at a theoretical 21 PB/s) stays “very unique” and competitive for super-fast servers, but “even if it's SRAM, 44 GB isn't really cutting it anymore.” A WSE4 announcement is the fingers-crossed scenario.

5. The unanswered macro question

  • The narrator leaves one question hanging after the rundown: “Right now, all lines are only going up, but for how long?” That leads into SemiAnalysis's Accelerator and HBM model tracks and the free Inference X dashboard, which covers real-world accelerator benchmarks.
Speaker 1

2026 will be a massive year for AI hardware, no matter whether we're talking about GPUs, ASICs, or beyond. I'm not sure we can still call this an emerging industry. Google's first TPU was released in 2015, over a decade ago, and NVIDIA will celebrate its 10-year AI anniversary next year because Volta, the first Tensor Core GPU, launched in 2017. So it's settled: this is not a new industry anymore, but there are plenty of new chips. Here are, in no particular order, the most interesting AI chips for 2026. Let us know which chip you think will come out on top, and leave a comment if we missed a chip you think deserves to be in the next video.

1. Qualcomm Targets Inference

Let's start with a company and a chip whose first major deployment was recently announced. What was deployed, you ask? It was 3-year-old hardware based on an almost 6-year-old architecture. I'm talking about Qualcomm finally deploying its AI 100 chips at scale, even if the scale was small. Installing a cluster of 1,024 AI 100 chips doesn't matter in 2026. But what might matter is the new AI 200 chip Qualcomm announced in October last year.

With about 70 billion transistors produced on TSMC's N3E and 768 GB of LPDDR5X memory, the AI 200 ASIC is clearly designed for inference. Betting on LPDDR5X instead of supply-constrained HBM might have been a great idea 1 year ago, but memory prices are skyrocketing across the board, including LPDDR5X. It's unlikely that AI 200 will make major waves this year, but its successor, AI 250, is supposed to come with a new compute-near-memory architecture. According to Qualcomm, that results in a 10x increase in effective memory bandwidth.

Paired with fast next-generation LPDDR6 memory, there might be something worthwhile on the horizon. So don't put on your party hats just yet, but do keep Qualcomm in mind.

2. AMD Builds A Challenger

If NVIDIA is Goliath, this company would be David. At least, I'm sure that's what AMD would like to hear. AMD is the second major player in the GPU space, and 2026 could be a turning point if MI455X and the Helios Rack are on time. MI455X is based on the new CDNA 5 architecture and packs 320 billion transistors into a mix of 12 2-nanometer and 3-nanometer logic chiplets connected via advanced 3.5D packaging. But the biggest selling point could be the massive memory setup.

MI455X comes with 432 GB of next-generation HBM4 and a bandwidth of almost 20 TB/s. There's much more to MI455X and the Helios Rack than we have time for this video. If you want to know how AMD is challenging Nvidia, check out the semi-analysis article on AMD's AI strategy. It not only offers a deep dive into MI455X, but also explains the Helios Rack architecture. It's definitely worth a read. I'll drop a link in the video description below.

3. Google Extends TPU Access

Google is truly the grandfather of AI. Not only was “Attention Is All You Need” basically a Google paper, but TPUs have been kicking it since 2015. While everyone was hyped about blockchains, Google was already preparing for AI. Ironwood, aka TPUv7, is built on TSMC's N3E with very likely more than 100 billion transistors. It has, of course, 2 large compute chiplets and comes with 192 GB of HBM3E. It's specifically designed to run Gemini inference.

But Google's superpowers are the so-called optical circuit switches. These are tiny physical mirrors that allow for a fast and super-efficient optical interconnect. Google uses them to create superpods. These superpods connect up to 9,216 TPUs. My further reading recommendation is, as usual, the SemiAnalysis TPU V7 deep dive. TPUs offer a completely different approach to AI workloads and have a very different TCO metric. Link in the description below.

TPUs have always been at the forefront, but so far they were only used by Google. This changes with Ironwood. The question is whether external customers can use them as well as Google can. If so, Ironwood will be a heavyweight for efficient and low-cost inference.

4. Specialized Chips Trade Speed for Scale

Another chip that isn't really brand new but is still hot for 2026 is Cerebras' Wafer Scale Engine 3, or WSE3. It was launched back in 2024, but new clusters have just recently been announced. WSE3, as the name implies, uses an entire silicon wafer to create a massive chip. It contains an unimaginable amount of SRAM. No, not megabytes. I'm talking about 44 GB and a theoretical memory bandwidth of 21 PB/s. But remember, we are talking about an entire wafer.

Based on the slightly older N4P node, it contains a whopping 4 trillion transistors. Everything about WSE3 is extraordinary. Even if it's SRAM, 44 GB isn't really cutting it anymore. It's still a very unique concept and competitive when it comes to super-fast servers. While WSE3 could be the odd one out in 2026, we might see an announcement of WSE4. Fingers crossed.

Groq is an interesting one, not to be confused with Elon Musk's Grok AI model. The one I'm talking about has a Q, not a K. And that Groq with a Q was acquired by NVIDIA. We don't know for sure if there will be a 2026 product or if it's more of a foundation for the future, but I still wanted to mention it because it's a very cool concept.

The Groq Language Processing Unit, or LPU for short, has relatively unspectacular specs: 55 billion transistors on a 14-nanometer GlobalFoundries node and no external memory at all. Nothing to write home about, it seems. But the LPU doesn't need any of that. It has 230 MB of ultra-fast SRAM placed very close to the compute cores. The chip is designed in a way that every step, every calculation, runs like clockwork.

This is called deterministic execution, and it basically eliminates the latency problems that GPUs have to deal with. But because you have so little memory, you need to connect a lot of LPUs to run even smaller models. Everything is a trade-off. No matter what, NVIDIA thought it was worth about $20 billion. I'm excited to see what the 2nd-generation LPU based on Samsung's 4-nanometer process can do, and what NVIDIA does with it.

5. NVIDIA Raises the AI Bar

I can't avoid the elephant in the room any longer. NVIDIA is number 1 for a reason, and with Vera Rubin, NVIDIA is taking the next step, moving to TSMC's N3B and HBM4. A single VR200 can crank out an insane 35 petaflops of FP4 per package. Combined with 288 GB of ultra-fast HBM4 at 22 TB/s of bandwidth—or at least that's the speed NVIDIA is targeting—a single superchip is already a force to be reckoned with.

But combining 72 of these in the NVL72 rack using NVIDIA's NVLink scale-up network, Vera Rubin will very likely once again top the charts. Or will it? MI455X does have a memory advantage, at least until Rubin Ultra, which will come with a full terabyte of HBM. No matter what, there's no doubt that VR200 is the most anticipated release for 2026. And it's also the topic of the latest semi-analysis article, just in case you really want to know how Vera Rubin is built and how it works.

6. Hyperscalers Build Custom Silicon

Mark Zuckerberg is on a massive spending spree. Meta is basically buying everything it can, and that includes GPUs from NVIDIA and AMD, and even TPUs from Google. This makes it easy to forget that Meta has its own silicon. The Meta Training and Inference Accelerator, or MTIA for short, is now in its 3rd iteration. We don't know all the specs yet, but it will be produced on TSMC's N3P with very likely more than 100 billion transistors and HBM memory.

Previous MTIA versions still use LPDDR5X. Meta knows exactly what its internal workloads need, and those workloads aren't only AI chatbots; they're also AI recommendation models that run the algorithms for Facebook, Instagram, and Threads. MTIA V3 won't be Meta's chip for AGI, but it offers good margins for its business model.

That means Meta can use all the external hardware to train new models while internally switching to its own silicon for inference. Looking at the roadmap, we will see a lot more MTIA in the future.

There's a lot of AI silicon, but only a few chips see truly large-scale deployment. One of them is Amazon's Trainium. There are hundreds of thousands of Trainium 2 chips deployed inside AWS AI data centers in Canton and New Carlisle, which makes Trainium 3 a top contender for future large-scale deployment. Trainium 3, despite its name, combines training and inference capabilities in a single chip.

Built on TSMC's N3P, it consists of about 125 billion transistors and comes with 144 GB of fast HBM3E. You can find much more, including TCO numbers, in the semi-analysis Trainium 3 deep dive. And yes, it's an actual technical deep dive. Anthropic's amazing Claude Code was trained on and runs on Trainium. It can only get better with Trainium 3. And Anthropic isn't the only fan. OpenAI will use 2 GW of Trainium compute starting this year. If you're looking for an ASIC with truly large-scale deployment, look no further than Trainium 3.

Microsoft's first ASIC, Maia 100, was a little bit of a mystery. Like every new in-house design, it had to prove itself first. Does it warrant a 2nd generation? With Maia 200, we have the answer. At around 825 mm², the almost reticle-busting chip contains 140 billion transistors, is manufactured on TSMC's N3P, and comes with a pretty large 216 GB of HBM3E.

Maia 200 will be used for inference and is optimized for FP8 and FP4, providing over 5 and 10 petaflops, respectively. Microsoft will use it for its in-house models, but Maia 200 will also run future ChatGPT models. More and more inference is moving away from NVIDIA to custom silicon.

7. Intel Tries Again

Last but certainly not least, we have Intel, which is having another go at an AI GPU. But it doesn't seem like Jaguar Shores is targeting a 2026 release. With so many ASICs, I had to talk about one more GPU, even if it might be a 2027 product. Jaguar Shores comes with a pretty strong spec sheet: an 18A process node, 175 billion transistors, and 288 GB of HBM4.

On paper, it's competitive. But paper is patient. After many attempts, Intel not only has to prove it can build and produce an AI GPU, but also provide the proper software support. No matter what, a third player in the GPU space would be very welcome. Jaguar Shores will show whether Intel can compete again.

The chip wars are heating up, and what we just talked about is only a small selection of the entire market. If you compare this list with what the Semi Analysis Accelerator and HBM model tracks, you will know what I mean. Right now, all lines are only going up, but for how long? If you are working in or with the industry and are interested in a clear picture view of the entire AI silicon market, and where it's headed, the Semi Analysis Accelerator and HBM model is your best choice. Not only does it offer a comprehensive overview of all current and future chips, it also provides shipment numbers and ASPs. Plus, deep insights into the HBM market. You can find the link in the description below, right next to all the deep dive articles we talked about in the video. And if you are less interested in specs, but more in real-world performance, Inference X offers comprehensive benchmarks across a wide range of accelerators. Because, what really matters in the end is how a chip performs. Check out the Semi Analysis Inference X dashboard. It's free. You know where you can find the link. I hope you enjoyed this video, and see you in the next one.

AI Chip & Silicon Round-up 2026 | BidClub