Ep. 040 - ASML Is Building a Hybrid Bonding Tool, and We Have the Patents (AI Supply Chain)

We traveled back to Portland to tear down this phone.

Yeah.

We brought one sample back to Singapore for testing.

What do you mean? You’re going to plug it in in Singapore?

Yeah, and do benchmarks on it. This Huawei phone opens up.

Are you then going to plug a SIM card in it and do some qualitative testing as well?

Yeah, maybe. After that, we might sell it.

Yes.

Or if the teardown team needs another sample, in case anything goes wrong, this is a backup.

You keep the backup teardown in your back pocket?

Hello, everyone. Welcome back to SemiAnalysis Weekly. This is Jordan. I’m here with Howie and Sherry. And in this episode, we’re going to be talking through an article that was just put out called “ASML Is Building a Hybrid Bonding Tool.” Big news. It hasn’t been announced yet, but we’ve got the patent filings, we’ve made some annotations, and we’re going to talk to the experts. So, guys, welcome to the show. Excited for this one.

Yeah, thanks for having us on.

Thanks, Jordan.

Okay, so take me through it. When did you guys first discover this, and what were the initial conversations about as you were getting ready to write this article?

The main thing was a tip-off from this great guy on Twitter called Lithos Crafty. He made a great series of tweets. I’m not sure how he found the patent, but it’s been there for a while, actually, this 2025 patent. It shows a specific and unique strategy for integrating ASML’s strengths and applying them to hybrid bonding.

From there, we did a bit more research into the startup SuperTrak, which is engineering this conveyor system. Then we dug in and compared the differences. It’s definitely not going to happen anytime soon, right? It’s several years out, but it’s at least worth discussing because it’s very different from all the current tools out there.

Yes. In fact, we started looking into this a long time ago. There was an advanced packaging series that Dylan and other teammates wrote back in 2023 or even earlier. We started focusing on this area a long time ago, which is why any news in this segment interests us.

Makes sense. What’s the high-level difference? Maybe some people listening don’t understand hybrid bonding. Can you give us a high-level introduction, and then we can talk about the specifics?

On a very high level, a traditional tool from companies like Besi for a die-to-wafer system, which is what this is going to be, uses a static wafer as the base wafer. In hybrid bonding, for example, you have a top die and a bottom die. The base wafer is the target, and a pick-and-place machine takes the chiplets for the top die, aligns them, and places them onto the base wafer to make sure they’re properly aligned.

Before that, there are several preparation and measurement steps to make sure everything is aligned. After that, there are other steps for hybrid bonding, such as annealing and processing. Those won’t be covered here, but the main tool we’re talking about is the pick-and-place tool.

What ASML is doing differently with this patent is trying to integrate some of the metrology features into a conveyor-belt system. Instead of the dies being picked and placed onto a wafer, they go around a carousel on a track, passing through various stations for measurement and plasma activation. Finally, they go down to the bonding station, where the wafer comes up toward the die and meets it at the carousel. That’s where the bonding happens.

With this specific method, ASML can use several of its competencies in measurement metrology and wafer-stage handling. The wafer moves toward the die rather than the die moving toward the wafer. That’s the main difference.

Makes sense. You speculate that they could be building a wafer-to-wafer hybrid bonding tool as well. Can you describe the difference between die-to-wafer and wafer-to-wafer?

Sherry, do you want to take that?

Sure. Wafer-to-wafer is basically bonding 2 wafers together, whereas with die-to-wafer, as Howie described, you first have a die and then put it on the wafer. Die-to-wafer is more challenging than wafer-to-wafer because there’s a higher requirement for alignment. Also, right now we lack mature tools that can meet both the accuracy and throughput we need.

Based on the patent filings, there are reasons to believe ASML is building both, but there are more patents about the die-to-wafer tool they’re building. We believe that when ASML enters a market, given its competitive positioning in lithography, it aims to be the most advanced and the best. That’s why we think they could be building both, but the patent filings suggest they’re moving ahead with die-to-wafer.

Okay. Can you tell me a little bit about what the existing tools are? You mentioned Besi, for example. It won’t just be ASML building a hybrid bonding tool, right?

That’s right. The current state of the art is from companies like Besi and ASMPT, among others. They come from a pick-and-place background. What they used to do well, and what they still do very well, is pick and place individual, small chiplets.

The placement arm—the mechanical arm with stepper-motor controls and things like that—is very good at achieving the overlay from the die onto the base wafer and then placing it down. It doesn’t use any force; it just places the die onto the bond pads. The bonding step comes later, when you do the anneal. That’s the current technology and state of the art.

However, ASML is coming from a different place: the front end. Its tools are regularly used for sub-nanometer alignment and overlay. When you’re trying to manufacture intricate transistors or do lithography patterning, you need extremely fine-grained control. It’s easily an order of magnitude higher precision.

From ASML’s perspective, if it already has this capability, why not find a way to implement it for hybrid bonding, especially now that hybrid bonding is moving to finer and finer pitches? The hybrid-bond pitch—how many signals you can get per square millimeter going between the 2 dies—is becoming more and more important. By coming at it from a front-end perspective, ASML doesn’t have issues with overlay. Its challenge is how to implement its capabilities in a system that can bring the dies to the wafer or, in this case, the wafer to the die. It’s a pretty novel solution, and we also discussed some of the challenges they might face compared with current technologies.

Yeah. But let me take a step back. You guys mentioned this article at the beginning, right? This was February 2024, so coming up on 3 years ago. In the description of this article, you’re talking through exactly what hybrid bonding is and discussing AMD 3D V-Cache. Obviously, now, if I go back to the present day, there’s a claim in here that HBM will not adopt die-to-wafer hybrid bonding before 2029, if at all. Can you talk about the implications of hybrid bonding, where you think it’s going to fit in, and the reasoning behind that?

I would say the primary purpose of hybrid bonding is for logic. It allows you to partition the IP—all your different functional units—into 2 separate layers. Putting signal wires between the units to communicate is a much shorter distance if you place them above each other, and you can have many more wires. If you place them next to each other, you’ll have some kind of limit on your data fabric: how quickly or efficiently one segment can talk to another.

I have an example right here. This is the Huawei C2 phone, and inside is the 9050 chip. It’s the first mobile phone to use hybrid bonding and 2 separate wafers, 2 layers, to split the IP and get the most out of the process technology they have. A case in point is logic: power efficiency and increasing the effective area budget in the limited size of a phone. That’s the main use case we see so far.

On the memory side, the claims about using hybrid bonding for HBM are primarily about packaging. It’s about how many layers of memory you can stack into a given maximum thickness, because a silicon wafer has a maximum thickness of 725 microns, slightly less than 1 millimeter.

And people want more and more capacity, right? So if I use hybrid bonding, maybe I can have 50% more gigabytes of HBM stacked in the best-case scenario. Memory vendors have been putting a lot of R&D and marketing into hybrid bonding. But the ROI isn’t there because, fundamentally, hybrid bonding is a much more expensive process to implement than traditional reflow or thermal compression bonding (TCB), which is what they are currently using for HBM.

There’s a small benefit to thermal performance and perhaps to signal integrity. However, the main thing is just to get the density up. Right now, that is not the priority of most AI labs or most HBM requests. We have been asking, and the memory vendors have received a lot of requests to reduce the number of layers for a given performance and bandwidth. So this is currently pushing back the need for that many layers. If you don’t have to use hybrid bonding, then you shouldn’t. That’s why we’re also making the claim that it isn’t going to come anytime soon in high volume for HBM. It will mostly be for logic.

Sherry, do you agree with all that? Does that make sense?

Yeah. I think what Howie mentioned—and, in fact, we have written a detailed article about the HBM spec. In that, we have run through the economics of whether it makes sense to continue stacking more, or for the time being, use what we have right now: 4-high. If you read through that, you also get more color on why there’s a delay with HBM right now.

On top of that, what we just mentioned about die-to-wafer hybrid bonding being more challenging in terms of the accuracy it requires and the throughput—all these factors combined lead to the delay that we believe will happen. That’s why our timeline for adoption is 2029 or beyond.

Yeah. This is quite a big difference. It’s not like all adoption of new tools in the fabs has come quickly or on time in the past. But just looking at this ASML roadmap, which was published in 2024 and which you guys cite in the article, there’s a lot of “hybrid, hybrid, hybrid, hybrid, hybrid” across NAND and DRAM.

And of course, ASML likes to have an optimistic prediction of technology and computation because they want to sell more tools. They want extra complexity, right? I remember very famously that they had a transistor-density metric and a graph showing High-NA adoption, and the density numbers were totally off the charts: 300, 400, 500 million transistors per square millimeter, which is nowhere near what we even have to this day. So, do take those with a pinch of salt.

Makes sense. Okay, so maybe we can dig into the actual tool itself and what’s so unique about it. I can start by throwing the patent diagram you guys annotated back on screen. Maybe you can talk through a little bit of this.

I’ll start, but then I’ll let Howie continue, because I still remember the day we were looking at the graph and how you were describing how the track runs through. There’s also an important part of the ecosystem change that’s needed, and I’ll let Howie review that.

What’s really unique is that normally what we see on the market right now are chamber tools, which means the tools don’t move; the dies move to different stations and get processed. But, as you pointed out here, the unique thing about this tool is that, when we read the filings and patents and look at what ASML draws, it should be running on a track. They’ve named SuperTrack Conveyance as a company or potential supplier to provide the track.

The fundamental difference, as we pointed out, is that for a BESI-type tool, the die is prepared elsewhere, and the bond head picks up the tool and puts it at the stations for final placement. But in ASML’s design, the die sits on its own holder and stays there as it moves through different stations. It only leaves at the bonding step. I’ll let Howie describe the other parts of the track and other tools that could potentially be interesting or challenging.

The super interesting part here is that the die isn’t moving from the conveyor belt. The die stays on the conveyor belt. How the die gets onto the carrier doesn’t matter too much, because the subsequent stations will measure how the die is oriented on the carrier and make a compensation later, at the bonding step.

The main difference here is that each tool function—each so-called chamber—has to physically come down and approach the die. Even during bonding, the wafer has to come and approach the die on the carrier. Everything has to come to the die in question: the small chiplets.

How do you design a system where your normal metrology, your measurement tools, now need to operate in a moving scenario? They have to come down to engage with the die and the conveyor system. This is going to be pretty interesting to see how they implement it. Of course, it’s a nonstandard form factor. You’ll need some kind of co-design agreements with several companies that do the pre-bonding phase so they can integrate their functionality into this track system.

Of course, ASML could do everything themselves, especially on the metrology side. They shouldn’t have a problem there. But the challenge is: how do you maintain measurement accuracy when the tools themselves start moving to approach the die? That’s going to be a big question.

Another question is how you maintain cleanliness over such a huge surface area. Imagine your current tools. Although this isn’t the kind of clean room used for front-end transistor formation—not that level of cleanliness—even so, how do you make sure that when the die moves between the different stations, the track, which spans several meters and several square meters of area, isn’t exposed? How are they going to contain it as the die moves between the tools and as the chamber comes down to approach the die? How does it handle the air and the environment? That’s going to be a very interesting question.

Yeah. The critical thing you guys pointed out in the article is that a single particle between two wafers can unbond the area and result in a defective bond. You specify alignment accuracy and cleanliness. Can you distinguish between the two and explain how they might both come into play? Then maybe later we can talk about why ASML is set to benefit, because they have some experience keeping things clean.

Yep. The two major things are alignment and cleanliness. For alignment, you have to measure where the bond pads are relative to where you expected them to be, then make the relevant changes to the positioning. When the wafer approaches the die, you want it to compensate for any deviations—not just in the X/Y position, but also along the rotational axis and even out of plane. The die might be slightly tilted to one side, at an angle. So we’re talking about six degrees of freedom in terms of how the die can be aligned.

That comes under the purview of having structures on the die that you can measure. Then you know the die’s specific orientation on the carrier, on the conveyor belt. On the wafer, you need to know the position of the grid lines of all the different dies relative to 3D space. When you bring the two together, you have to make sure they come together vertically and are aligned on the XY plane. That is the main goal of alignment accuracy: like overlay, and then you can bring the two surfaces into contact.

The second thing is cleanliness. Hybrid bonding requires extremely flat surfaces, and they have to be free of particles because the bonding is oxide bonding from the dielectric, followed by an anneal where it gets heated and baked. Then the copper expands and fills the remaining gap. If you have any particles in between, it won’t just affect the bond in that area. The silicon will lift up and cause a defect across the whole area. It’s almost like forming a wedge: when you have an impurity, the whole surface can’t bond properly because something is in the way.

Making sure that when it’s clean at one station, by the time it arrives at the next station, it’s still clean is very important.

The alignment, accuracy, and cleanliness basically determine the bonding yield, which is very important because, ultimately, when we use the tool, we want it to have good yield and generate good throughput. Those high requirements also make hybrid bonding almost a front-end process, which is why we’re seeing more and more front-end tool makers. It’s not just ASML. Hybrid bonding matters globally, but it matters even more for China, since they’re leveraging hybrid bonding and advanced packaging as alternative ways to shrink.

We’re also seeing major Chinese semicap companies move into hybrid bonding or grow their advanced-packaging tool capabilities. NAURA and AMEC have both made moves by acquiring or investing to build those capabilities.

Can you explain that a little more? What do you mean when you say hybrid bonding can take the place of shrinking logic nodes? You don’t need high-NA tools or EUV if you’re—Here, Howie’s holding up the Huawei phone again. If you’re going to build a phone like that, with hybrid bonding you can still make it perform better.

The main thing is that, given their limitations in process technology and what’s available to them, they have to ask: How do you maximize performance? How do you keep increasing performance per watt? One very easy way to do that is to make the die bigger: use more silicon, run it at a lower voltage and lower power. That’s a very naive way to look at it, but having more silicon available can help increase power efficiency.

Hybrid bonding is a better version of that because the 2 layers of silicon are right next to each other, with a lot of wires connecting them. Given the limitations on the process technology they can apply, hybrid bonding and advanced packaging are another avenue for them to continue scaling. That’s why there’s a lot of demand in China.

Okay. Maybe we can go a little more technical. Why exactly do you think hybrid bonding allows them to improve performance per watt or performance per square millimeter?

A key example Huawei has given, which we also see in this phone, is that you’re able to split certain components, certain functional units within the core. For example, you can place the components that require high speed closer together, so there’s less timing delay and less congestion when they communicate with each other.

They’re able to be placed closer together because other noncritical components, like SRAM or memory cells, can be placed on the bottom die, on a different layer, and are out of the way. That puts the important components closer together and can, for example, improve the clock speed. They get up to 2.7 GHz without increasing the voltage or power.

In a general sense, just having more silicon and more area budget for a given power envelope usually gives you slightly higher power efficiency for the same architecture. Running more silicon at a lower voltage means less leakage, so less power is wasted transmitting signals from one end to the other. That’s why hybrid bonding helps in this sense.

Makes sense. Sherry, can you explain a little about the implications for China that you’re referring to? Does this imply that a hybrid bonding tool wouldn’t be subject to export controls, or that you think it’s within the scope of what a Chinese tool maker would be able to produce themselves?

What we’ve seen, as we also mentioned in the article, is that BESI is the leader in die-to-wafer bonding. For wafer-to-wafer bonding, there are more players, like EVG, ASML, and PDN, but international incumbents still dominate the field for now.

We’re seeing China’s major semicap companies grow their capabilities. We believe, as with other tools, that geopolitical complexities could drive the need or motivation to develop homegrown tools. China is always motivated to build its own supply chain, which is why we’re seeing more initiatives by Chinese tool makers to grow these capabilities.

You can see it in the roadmaps, too, in how aggressively they’re implementing hybrid bonding. Look at the data center side: they’re working very hard to overcome power-density limitations. They want to implement hybrid bonding and have what they call “logic folding”—a full hybrid-bonded design for data center accelerators by 2030.

We’re talking about much higher densities than TSMC’s SoIC, in terms of bond pitch. Given the demand and their process limitations, they’re looking not just at the current 2 layers, but even 3 layers by 2030. That would reduce yield further, which means you need more tools to get the same yielded output. There’s a lot of demand in this area.

Okay. Something you mentioned in passing in the article caught my eye: the joint initiatives between ASML and TSMC, IFS, and Samsung to move from 6-inch to 12-inch photomasks for High-NA EUV tools. Can you give me the high-level implications? This isn’t coming soon, but it seems like it would allow similar improvements, such as increasing die size.

The main limitation of High-NA is that your reticle size is cut in half because the anamorphic lens squeezes the mask pattern 8 times in one dimension, but only 4 times in the other. That leaves you with a maximum die size of around 400 square millimeters, versus about 850 square millimeters currently.

To get a full-reticle-size design, you can use a modified kind of stitching. IMEC and ASML talk about delineating a specific region in your floor plan, in your chip design, where you know there’s going to be some stitching. You can either use other layers—non-High-NA layers—to do the stitching, or dedicate a specific area to it.

That’s what will happen in the interim. Then, in the 2030 timeframe, we’re looking at a 6-by-12-inch mask. The mask is now double the length in one dimension, so when it’s reduced 8 times in one direction and 4 times in the other, you get back the full reticle. That eases a lot of the headaches and improves throughput even more. ASML is focused on high-productivity tools, and this extends that approach: you get the full mask size on High-NA, freeing up the design and allowing higher throughput with the full reticle.

One point is the ecosystem. This has implications for the entire ecosystem, because it’s not just ASML or the mask makers that have to change; it’s the entire supply chain. That’s why this takes time. ASML also took time to work with the fabs to get this started, given the complexities of the supply chain.

The second point Howie touched on is throughput, which is very important for ASML. Management mentioned on a recent earnings call that its pricing is basically value-based. As throughput increases, that also drives up pricing, which will be beneficial for them longer term.

Interesting. Makes sense. Can you dig one layer deeper into the supply chain implications? Maybe you covered it in the research and shouldn’t talk about it now—in that case, excuse the question. But if not, at a high level, what’s technically changing in the supply chain that you think would have implications?

The main thing is that the entire mask inspection, production, and protection with the pellicles all need to be updated to fit this larger 6-by-12-inch mask. A little fun fact: it’s not actually 12 inches; it’s about 11.2 inches or something like that, so the mask blank fits in the current FOUPs and overhead material-handling systems. But it’s still large enough to fit the larger mask pattern.

That’s just one example. All your carriers—how do you carry the mask? Then there are your pellicles. If you have a double-size mask area, all your e-beam metrology and inspection, and mask repair, are going to be even more complex. The whole industry needs to agree on how we’re going to approach this larger mask size.

It’s very akin to wafers going from 8-inch to 12-inch back in the early 2000s. We’re looking at the whole industry needing to move together, and that’s why you need this kind of early commitment from all the foundries and ASML to ensure everyone is coming up to speed in the supply chain.

It does make me think a little bit about what you were talking about earlier: China could be more aggressive in going for hybrid bonding and building an ecosystem around that, which could create even more of a split, where ASML and the foundries that run their tools end up pushing further on High-NA and making some decisions there. But then you mentioned that you get the reticle size back, and I’m wondering if somehow they wrap around to the same thing for chip designers, where designs used on one can now be more transferable to another stack of tools in some way. I assume that’s probably not the case.

Anyway, give me your high-level reaction to that. Do you think we should expect, with more export controls and all the geopolitics at play, that there will effectively be 2 separate tool stacks to build a fab on going forward? There’ll be one side pushing on hybrid bonding and the other side pushing on larger photomasks and continuing to shrink everything?

I would already say that that’s happening on the EDA side, on the chip-design side. The way you design a chip with multiple layers and partition which block should go where is something that everyone else hasn’t really had to deal with. China is pushing very hard on this, so Huawei has teamed up with several design companies to integrate and do the partitioning for the different functional groups.

On everyone else’s part, AMD is the original user of this SoIC hybrid bonding, but its partitioning is a lot simpler. It’s just looking at the L3 caches, SRAM, and so on. The split line between the different layers is also very distinct: the CPU cores go on one layer, and the memory goes on another. Whereas in the logic-folding hybrid bonding case, within the core you have all these little functions—for example, multipliers, timing relays, and buffers. All the small components that make up the core are being partitioned across the 2 layers.

This kind of very advanced design flow is already happening. This split is between the current Western EDA tools, which have never needed to do this in the first place, and the tools China has started developing on its own. I can at least speak to the design side, but Sherry can speak a bit more about the supply chain and manufacturing side.

In terms of the supply chain, we’ve talked about how there are multiple drivers for China to build its own supply chain or try to accelerate it as much as possible. We’re not experts at predicting what the policies could be, but what we’re seeing on the ground in China is that the companies themselves are driving this. Starting from this year, the domestic sufficiency initiative, which used to be state-led, is moving toward a stage where it’s more coordinated among the toolmakers and the fabs themselves.

They’re working together to design and build the tools, semiconductor capital equipment, and EDA. What China needs could be different from what the rest of the world needs, given some of the constraints it faces. We believe that process and effort won’t be affected by policies such as export controls. In fact, as we’ve seen with China’s semiconductor-capital-equipment localization rate over the past few years, export controls could accelerate that, push them, or increase their motivation to work harder on it. That’s what we’re seeing right now.

Makes sense, guys. I’m roughly out of questions. Maybe the only thing left that jumps to mind is what’s left for ASML to prove as it develops the hybrid bonding tool. We know you kept that behind the paywall, so we’ll skip it for now and say anybody interested in answering that question should subscribe to the research, check out the wafer fab equipment model, and reach out and let us know if they have any comments about this. Any final thoughts before we wrap up?

Yeah, I’m looking forward to our teardown of this.

Teardown of the Huawei phone. Let’s go. We published some good stuff previously on both of those, Intel and Huawei process, which is awesome. Sherry, anything from you?

I think it’s always great to work with great colleagues like Howie and Jordan, because every day I feel like the learning curve is 90 degrees here. I hope our readers also enjoy the technical part of our research. We’ll do more and update you again on ASML or other parts of the supply chain.

Awesome. Nice job, guys. Thanks for joining today.